One DRAM configuration utilizes an even number (such as two or four for example) of memory arrays arranged in pairs, with bitline sense amplifiers placed between each pair. The DRAM 10 in FIG. 1 illustrates such configuration. A pair of memory arrays 11 and 12 are shown with bitline sense amplifiers 13-i in between. Each bitline sense amplifier is connected to two pairs of bitlines, one pair from each memory array. For example, bitline pairs 11-3 and 12-3 in memory arrays 11 and 12, respectively, are connected to bitline sense amplifier 13-3.
Each of the pairs of bitlines 11-i and 12-i is connected to the respective bitline sense amplifier 13-i via a pair of select transistors not shown. The select transistors are used to connect either the bitline pair 12-i in memory array 12 or the bitline pair 11-i in memory array 11 to the sense amplifier 13-i.
A column decoding circuit (not shown) is used to select one of the bitline sense amplifiers 13-i, and provide a connection between the output terminals of the selected bitline sense amplifier and the data bus lines DB.sub.n and DB.sub.n. The I/O sense amplifier 20 is used for further amplification of the signals on DB.sub.n and DB.sub.n lines prior to transmitting these signals to an output buffer (not shown)
Accordingly, upon selection of a particular wordline in one of the memory arrays, a memory cell (representing one bit of information) from one of the two memory arrays 11 and 12 is selected. The state of the selected memory cell is sensed and signals representing this state are then provided on data bus lines DB.sub.n and DB.sub.n.
Another DRAM configuration, shown in FIG. 2, utilizes what is known as a staggered bitline sense amplifier architecture. Unlike the DRAM configuration shown in FIG. 1 wherein all bitline sense amplifiers are arranged between pairs of memory arrays, in FIG. 2 the bitline sense amplifiers (shown as 43-i, 44-i and 45-i) are arranged in a staggered configuration with respect to each memory array.
Bitline sense amplifiers 44-i are utilized in a similar manner to those in FIG. 1. Bitline sense amplifiers 44-i are located between and shared by the two memory arrays 41 and 42. Each of the bitline sense amplifiers 44-i is connected to two pairs of bitlines, one pair from each memory array. For example, bitline pairs 404A and 404B in memory arrays 41 and 42, respectively, are connected to bitline sense amplifier 44-2.
Bitline sense amplifiers 43-i and 45-i are located on the left side of memory array 41 and the right side of memory array 42, respectively, and will be referred to as the end-cap bitline sense amplifiers hereinafter. As shown, each of the end-cap bitline sense amplifiers 43-i and 45-i are connected to one pair of bitlines in the memory arrays 41 and 42, respectively.
All bitline sense amplifiers in FIG. 2 are similar in that each bitline sense amplifier receives two pairs of bitlines. Since the end-cap sense amplifiers 43-i and 45-i only receive one pair of bitlines from the respective memory arrays, dummy bitlines (also referred to as end-cap bitlines) are used as the second pair of bitlines. For example, end-cap bitlines 401A and 403A are used as the second pair of bitlines for the end-cap bitline sense amplifiers 43-1 and 43-2, respectively.
As shown in FIG. 2, the bitline sense amplifiers 44-i are connected to every other pair of bitlines in memory arrays 41 and 42, while the alternate bitlines are connected to the end-cap bitline sense amplifiers 43-i and 45-i; hence the name "staggered sense amplifier" architecture. In this manner, half of the memory cells in memory array 42 are connected by bitline pairs (shown, for example, as 401C and 403C) to end-cap bitline sense amplifiers 45-i, while the other half of the memory cells are connected by bitline pairs (shown, for example, as 402B and 404B) to bitline sense amplifiers 44-i. The memory cells in memory array 41 are similarly connected to the bitline sense amplifiers 43-i and 44-i.
Typically, a memory chip consists of more memory arrays than those shown in FIG. 2. Such a memory chip would include additional memory array arrangements similar to that formed by the bitline sense amplifiers 44-i and memory arrays 41 and 42. Note that in such a chip, the end-cap arrangements shown in FIG. 2, i.e., the end-cap bitlines and the end-cap bitline sense amplifiers, are provided only once for each end of the overall memory block.
A specific memory location is selected by selecting the corresponding wordline and the appropriate pair of bitlines. As in any memory array, the wordlines in memory arrays 41 and 42 (not shown) extend across the array in the direction perpendicular to the bitlines. To read out a memory cell, one wordline is selected from among the wordlines in memory arrays 41 and 42. The selected word line activates one row of memory cells; however, only the memory cells connected to the selected bitline pair will be read.
Each bitline in memory arrays 41 and 42 is connected to a select transistor not shown. A bitline pair is selected by activating the corresponding select transistors. The activated select transistors provide a connection between the pair of bitlines and the input terminals of the corresponding bitline sense amplifier. In this manner a direct connection is provided between the selected memory cell and the input terminals of a bitline sense amplifier.
Upon sensing the state of the selected memory cell, the bitline sense amplifier provides signals on its output terminals representing the state of the selected memory cell. The output terminals of each of the bitline sense amplifiers are connected to a pair of data bus lines DB and DB via a second set of select transistor pairs not shown. These select transistors are part of a decoding scheme wherein by activating a pair of select transistors, a connection is made between the output terminals of a bitline sense amplifier and the corresponding pair of data bus lines.
The column decoding scheme activates a specific select transistor depending upon (i) the array within which the wordline is selected, hereinafter referred to as the selected array, and (ii) the selected bitline pair in the selected array. For example, if a wordline and the bitline pair 403C are selected from memory array 42, the pair of select transistors which connect the output terminals of the end-cap bitline sense amplifier 45-2 to the data bus lines DB.sub.R and DB.sub.R are activated.
As in the DRAM configuration of FIG. 1, once the data is provided on the appropriate DB and DB lines, a second amplification is carried out. The I/O sense amplifiers 60 and 70 perform this task. The I/O sense amplifier 60 receives DB.sub.n /DB.sub.n lines at its input terminals and provides a signal representing the state of the sensed memory cell on its output terminal DO.sub.n. The output terminal DO.sub.n is in turn fed to an output buffer circuit not shown.
Due to the staggering of the bitline sense amplifiers, a selection needs to be made between the DB.sub.L /DB.sub.L lines and DB.sub.R /DB.sub.R lines prior to amplification of the signals on these lines. Multiplexer 80 performs this selection in response to an asserted input signal &lt;A&gt; or &lt;B&gt; from the selected array 41 or 42, respectively. If input signal &lt;A&gt; is asserted, the signals on DB.sub.L /DB.sub.L lines are passed through for amplification. If input signal &lt;B&gt; is asserted, the signals on DB.sub.R /DB.sub.R lines are passed through for amplification.
I/O sense amplifier 70 then amplifies the signals on the selected data bus lines. I/O Sense amplifier 70 provides the amplified signal on its output terminal DO.sub.m. The output terminal DO.sub.m is in turn fed to an output buffer not shown.
The initial sensing performed by the bitline sense amplifier is in the critical speed path (what is commonly referred to as the "address access time") of the memory chip. Thus, it is desirable to minimize the time delay associated with amplifying and transmitting the small signal associated with the selected memory cells. However, two factors hinder reducing the time delay. First, the area within which each bitline sense amplifier is physically laid out is limited to the pitch of two bitlines. As such, the drive capability of the bitline sense amplifiers is severely limited because the transistors in the bitline sense amplifiers cannot be made as large as desired.
Second, since the output terminals of the selected bitline sense amplifier are connected to the corresponding data bus lines, the selected bitline sense amplifier is required to drive the capacitive loading associated with the data bus lines. The data bus line capacitance increases as the length of the data bus line increases.
The impact of the first factor, namely the area limitation, is reduced by staggering the bitline sense amplifiers. Staggering the bitline sense amplifiers doubles the space within which each bitline sense amplifier is laid out, i.e., within a pitch of four bitlines rather than two. However, the time delay degradations due to the second factor is further exacerbated because of the additional data bus line routing required in providing both sets of data bus lines DB.sub.L /DB.sub.L and DB.sub.R /DB.sub.R to the multiplexer 80.
In order for the multiplexer 80 to carry out the selection function, either DB.sub.L /DB.sub.L lines or DB.sub.R /DB.sub.R lines need to be routed across a portion of the chip, as illustrated in FIG. 2. The additional routing significantly increases the interconnect capacitance on the routed data bus lines, thereby degrading the address access time.
Furthermore, unlike the read path represented by DB.sub.n /DB.sub.n lines and I/O sense amplifier 60, the read paths represented by DB.sub.L /DB.sub.L and DB.sub.R /DB.sub.R lines include multiplexer 80. The gate delay associated with multiplexer 80 causes additional time delay.
Therefore, the capacitive loading due to the additional routing of the DB.sub.L /DB.sub.L and DB.sub.R /DB.sub.R lines coupled with the gate delay associated with multiplexer 80, degrade the overall speed of the DRAM device. These drawbacks hinder achieving the desired device address access times, specially in high speed DRAM designs.